The present invention relates to an apparatus and a method for inspecting an array substrate of a liquid crystal display (LCD).
An array substrate of an LCD in FIG. 3 is a well-known array substrate which comprises: a substrate; a plurality of gate lines 12 provided on the substrate; a plurality of data lines 14 that cross the gate lines 12 through an insulating layer; switching elements 16 provided near the intersections of the gate lines 12 and the data lines 14 and connected to the gate lines 12 and the data lines 14; pixel electrodes 18 connected to the switching elements 16; storage capacitor (Cs) lines that form storage capacitors 26 by facing a part of the each pixel electrode 18 through an insulating layer; and gate-electrode capacitors 24 formed between the gate lines 12 and the pixel electrodes 18. In this specification, the pixel electrode 18 is indium tin oxide (ITO).
Array substrates of an LCD are produced by etching and depositing various materials over and over again. They are inspected after the production, and non-defective ones are used in an LCD. As shown in FIG. 3, an inspecting apparatus 11 comprises: a gate voltage generating circuit 29 connected to a pad 34 of the gate line 12 through a probe 38; a write circuit 30 for applying a write voltage to the data line 14; a read circuit 32 for reading electric charges accumulated in the gate-electrode capacitor 24 and the storage capacitor 26; a switch 42 for selecting the write circuit 30 or the read circuit 32; and a probe 40 connected to the pad 36 of the data line 14.
In general, the voltage applied to the pixel electrode 18 is xcex94V lower than a desired voltage to be applied, depending on the storage capacitor 26 and a liquid crystal capacitor. Such voltage difference xcex94V is hereinafter referred to as a xe2x80x9cpunch-through voltagexe2x80x9d. If the punch-through voltages xcex94V of all the pixels are constant, the voltage to be applied to the pixel electrode 18 is increase by xcex94V so that all the pixels can function normally.
As the capacitance of the gate-electrode capacitor 24 increases due to foreign matter attached on the array substrate or defects in the array substrate, the punch-through voltage xcex94V gets higher than that of a normal pixel. This causes malfunctions of the LCD. For example, when electric charges are accumulated in the gate-electrode capacitor 24 and the storage capacitor 26 and then the switching element 16 is turned off, the electric charge accumulated in the storage capacitor 26 is transferred to the gate-electrode capacitor 24 and thus the storage capacitor 26 cannot retain desired electric charge.
If the amount of change in gate potential is xcex94Vg=(VGHxe2x88x92VGL) and a capacitance of a liquid crystal capacitor is Clc, the punch-through voltage xcex94V can be expressed by xcex94V=xcex94Vgxc3x97Cgd/(Cgd+Clc+Cs). In this specification, Cs and Cgd indicate capacitances of the storage capacitor 26 and the gate-electrode capacitor 24, respectively, VGH and VGL indicate a voltage to be applied to the gate line 12, and VGH is higher than VGL and turns on the switching element 16.
An electric charge Q is measured as follows. As shown in FIG. 4(a), an inspecting apparatus applies a gate voltage VGH. When the electric charges are written (T1), the conditions of the electric charges are expressed by Qgd=Cgd (VDxe2x88x92VGH) and Qcs=Cs (VDxe2x88x92VCs). In this specification, the phrase xe2x80x9celectric charges are writtenxe2x80x9d means that the electric charges Qgd and Qcs are accumulated in the gate-electrode capacitor 24 and the storage capacitor 26, respectively. In addition, VD indicates a write voltage to be applied to the data line 14 shown in FIG. 4(b) and Vcs indicates a voltage to be applied to the storage capacitor (Cs) line 20.
When the electric charges are retained (T2), the conditions of the electric charges are expressed by Qgd=Cgd (VITOxe2x88x92VGL) and Qcs=Cs (VITOxe2x88x92VCs), wherein VITO indicates a voltage to be applied to the pixel electrode 18.
When the electric charges are read (T3), the conditions of the electric charges are expressed by Qgd=Cgd (GNDxe2x88x92VGH) and Qcs=Cs (GNDxe2x88x92VCs), wherein GND indicates an earth potential.
The electric charge Q to be detected in the inspection of the array substrate are determined by subtracting the total amount of electric charges in a read operation from the total amount of electric charges in a write operation, and is expressed by Q=VD (Cs+Cgd). In the aforementioned expression, the capacitance of a data-electrode capacitor 44 shown in FIG. 5 is neglected.
If Cs is 0.1 pF, Cgd is 0.01 pF, and a write voltage VD is 10V, the electric charge Q to be detected in a normal pixel is 1.1 pC.
In a defective pixel caused by a punch-through voltage failure, Cgd is 0.02 pF which is twice as much as that in a normal pixel. However, the electric charge Q detected in that defective pixel is 1.2 pC. Thus, the difference in electric charge between the normal pixel and the defective pixel is less than 10%, which is not sufficient enough to judge that Cdg falls outside a normal range, allowing for noise of the inspecting apparatus itself.
Further, it is also difficult to detect a capacitance of the data-electrode capacitor 44 shown in FIG. 5 using the aforementioned technique, because no electric charges are accumulated in the data-electrode capacitor 44 in the write operation (T1) and therefore no electric charges are left in the read operation (T3).
More specifically, voltages to be applied to the gate line 12 and the data line 14 in the write and read operations are the same as those shown in FIG. 4. If the capacitance of the gate-electrode capacitor 24 is neglected, an electric charge Qw in the write operation is expressed by Qw=Cs(VITOxe2x88x92VCs)+Cdd(VITOxe2x88x92VD) and an electric charge Qr in the read operation is expressed by Qr=Cs(GNDxe2x88x92VCs)+Cdd(GNDxe2x88x92GND). In the aforementioned expressions, Cdd indicates a capacitance of the data-electrode capacitor 44. Therefore, the electric charge Q to be detected is expressed by Q=Cs(VITOxe2x88x92GND)+Cdd(VITOxe2x88x92VD).
If VGH is sufficiently high, for example, VD+5V or more, VITO=VD. Therefore, the electric charge Q to be detected is expressed by Q=(VITOxe2x88x92GND) and thus Cdd is not included. Since the capacitance of the data-electrode capacitor 44 cannot be detected during the inspection, even if the capacitance of the data-electrode capacitor 44 is not the normal value, the array substrate cannot be judged as defective.
Japanese Unexamined Patent Publication No. (Patent Kokai No.) 11-183550 (1999) discloses an apparatus for inspecting an array substrate. In this apparatus, an electric charge is accumulated in a pixel and then read after predetermined time. This is effective when a silicon etching residue is left between a pixel electrode and a common electrode. However, unlike the present invention, this publication does not disclose that a gate voltage is changed in write and read operations.
Accordingly, an object of the present invention is to provide an apparatus and a method for detecting a defective pixel caused by a punch-through voltage that cannot be detected by a conventional apparatus for inspecting an array substrate.
An apparatus for inspecting an array substrate according to the present invention comprises: means for applying a first voltage to switching elements so as to turn on the switching elements when electric charge is accumulated in storage capacitors and gate-electrode capacitors of the array substrate; and means for applying a second voltage having a different voltage value than the first voltage has to the switching elements so as to turn on the switching elements when the electric charge accumulated in the storage capacitors and the gate-electrode capacitors is read.
A method for inspecting an array substrate according to the present invention comprises the steps of applying a first voltage to switching elements so as to turn on the switching elements when electric charge is accumulated in storage capacitors and gate-electrode capacitors; and applying a second voltage having a different voltage value than the first voltage has to the switching elements so as to turn on the switching elements when the electric charge accumulated in the storage capacitors and the gate-electrode capacitors is read.
The present invention makes it easy to detect a capacitance of a gate-electrode capacitor, which was difficult to detect in a conventional invention, by applying a different gate voltage in write and read operations, and also makes it possible to detect a defective pixel caused by a punch-through voltage. Further, in the present invention, it is possible to detect the capacitance of the data-electrode capacitor by adjusting a gate voltage.